I’m personally excited about the actual engineering challenges that come next and think that all 3 big foundries have roughly equal probability of coming out on top in the next stage, as the transistors become more complex three dimensional structures, and as the companies try to deliver power from the back side of the wafer rather than the crowded front side.
Samsung and Intel have always struggled with manufacturing finFETs with the yields/performance of TSMC. Intel’s struggles to move on from 14nm led to some fun memes, but also reflected the fact that they hit a plateau they couldn’t get around. Samsung and Intel have been eager to get off of the finFET paradigm and tried to jump early to Gate All Around FETs (GAAFETs, which Samsung calls MBCFET and Intel calls RibbonFET), while TSMC sticks around on finFET for another generation.
Samsung switched to GAAFET for its 3nm node, which began production in 2022, but the reports are that it took a while to get yields up to an acceptable level. Intel introduced GAAFET in its 20A node, but basically abandoned it before commercial production and put all of its resources into 18A, which they last reported should be ready for mass production in the first half of 2025 and will be ready for external customers to start taping out their own designs.
Meanwhile, TSMC’s 3nm node is still all finFET. Basically the end of the line for this technology that catapulted TSMC way ahead of its peers. Its 2nm node will be the first TSMC node to use GAAFET, and they have quietly abandoned plans to introduce backside power in the generation after that, for their N2P. Their 1.6 nm node is going to have backside power, though. They’ll be the last to marker with these two technologies, but maybe they’re going to release a more polished process that still produces better results.
So you have the three competitors, with Samsung being the first to market, Intel likely being second, and TSMC being third, but with no guarantees that they’ll all solve the next generation challenges in the same amount of lead time. It’s a new season, and although past success does show some advantages and disadvantages that may still be there, none of it is a guarantee that the leader right now will remain a leader into the next few generations.
Intel’s packaging doesn’t seem to be that far behind TSMC’s, just with different strengths and weaknesses, at least on the foundry side. On the design side they were slow to actually implement chiplet based design in the actual chips, compared to AMD who embraced it full force early on, and Apple who rely almost exclusively on System-in-a-Package designs (including their “ultra” line of M-series chips that are two massive Max chips stitched together) where memory and storage are all in one package.
I’m personally excited about the actual engineering challenges that come next and think that all 3 big foundries have roughly equal probability of coming out on top in the next stage, as the transistors become more complex three dimensional structures, and as the companies try to deliver power from the back side of the wafer rather than the crowded front side.
Samsung and Intel have always struggled with manufacturing finFETs with the yields/performance of TSMC. Intel’s struggles to move on from 14nm led to some fun memes, but also reflected the fact that they hit a plateau they couldn’t get around. Samsung and Intel have been eager to get off of the finFET paradigm and tried to jump early to Gate All Around FETs (GAAFETs, which Samsung calls MBCFET and Intel calls RibbonFET), while TSMC sticks around on finFET for another generation.
Samsung switched to GAAFET for its 3nm node, which began production in 2022, but the reports are that it took a while to get yields up to an acceptable level. Intel introduced GAAFET in its 20A node, but basically abandoned it before commercial production and put all of its resources into 18A, which they last reported should be ready for mass production in the first half of 2025 and will be ready for external customers to start taping out their own designs.
Meanwhile, TSMC’s 3nm node is still all finFET. Basically the end of the line for this technology that catapulted TSMC way ahead of its peers. Its 2nm node will be the first TSMC node to use GAAFET, and they have quietly abandoned plans to introduce backside power in the generation after that, for their N2P. Their 1.6 nm node is going to have backside power, though. They’ll be the last to marker with these two technologies, but maybe they’re going to release a more polished process that still produces better results.
So you have the three competitors, with Samsung being the first to market, Intel likely being second, and TSMC being third, but with no guarantees that they’ll all solve the next generation challenges in the same amount of lead time. It’s a new season, and although past success does show some advantages and disadvantages that may still be there, none of it is a guarantee that the leader right now will remain a leader into the next few generations.
Packaging/interconnect tech is starting to be a big factor though, and TSMC is very strong in this area, no? They can lean on that.
Also its weird to even imagine Intel with big external customers…
Intel’s packaging doesn’t seem to be that far behind TSMC’s, just with different strengths and weaknesses, at least on the foundry side. On the design side they were slow to actually implement chiplet based design in the actual chips, compared to AMD who embraced it full force early on, and Apple who rely almost exclusively on System-in-a-Package designs (including their “ultra” line of M-series chips that are two massive Max chips stitched together) where memory and storage are all in one package.